This invention relates generally to hardware verification, and more particularly to a method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU.
Address generation (AGEN), address generation interlocks (AGI) and address generation bypassing (AGEN Bypass) are complex functions sometimes implemented in the Instruction Dispatch Unit (IDU) of a CPU. Typically, verification of these functions is performed in unit simulation. For example, verification in unit simulation includes: 1) driving random data on the bypass buses from sending units (e.g. Fixed Point Unit (FXU)); 2) Predicting when AGI & AGEN Bypass are going to happen in the IDU; 3) capturing the bypass data, and storing that into a single (software) copy of the general purpose registers (GPRs); and 4) using the GPR copy to compute a predicted AGEN, to compare against the hardware AGEN result.
However, this approach has drawbacks including requiring effectively duplicating logic in the IDU (the design under test) in simulation code, to predict. AGI and AGEN Bypass, which is not desirable (logic errors can be duplicated & thus masked in the simulation code). In addition, the AGI and AGEN Bypass logic is complicated, and thus requires a lot of code and effort to implement and debug in simulation, including a lot of designer time in explaining the design and looking at false fails, and other time consuming operations.